8 半导体产品的静电破坏故障分析：[13][14][15][16][17] 

8.1 检验人员的训练与经验是故障分析的关键。 
8.2 原设计厂商的配合才能快速正确的找到故障进而找出原因。 
8.3 半导体产品的静电破坏有前后段之分，前段因还没有封装，表面一定可以光学显微镜看得到破坏的痕迹，这时受过训练有经验的检验人员才能分辨出破坏的痕迹。
8.4 到测试站发现漏电的产品，都是已封好的了，如果X光检查没有机械性短路常会往静电破坏的方向去想，要进一步检查当然要把封材打开。 
8.5 如果有原设计厂商的指导也可透过电测的手法，利用一些对漏电流有影响的特性，量测出半导体在特定条件下电流一定的变化，或找到放电击穿生成的二极管来加以确认故障。 
8.6 打开后的样品要先以光学显微镜找破坏的痕迹，然而因有些伤痕很小，有时高倍数(1000倍)的光学显微镜都无法看见，就要倚靠电子显微镜(SEM)来搜寻被破坏的位置。 
8.7 有原设计厂商的指导接上适当电源或信号源就可藉液晶显示或者微光显微镜找到发热点。 
8.8 静电放电破坏的痕迹通常要有些经验才看得出来，其现象常会是线条边浅浅的斑，绝缘层中的导线熔融时热膨涨造成表面的裂痕一般都要靠电子显微镜才能分辨。 
8.9 以上所找到发热点或熔融裂痕位置要进一步藉离子束蚀刻(FIB)切断面进一步找出真正烧熔处加以确认。 
8.10 集成电路只有输出入端才会受到静电放电破坏。 

9 结论

静电防护的投资是无法估算还本效益，但是往往防止一次静电破坏就够本，只要有静电产生一定会造成破坏，唯一正确的作法：防护重于治疗，静电放电防制最重设备的维护保持静电消除设备正常运作，其次才是监测，藉高频电磁波探测可帮助找到放电位置并排除之。
虽然本文主要探讨静电放电对集成电路的破坏与防护方法，但大部份集成电路在测试出有漏电故障其实并非静电放电击穿所造成，晶圆从原料到制造所产生晶格差排及微污染才是占大比例的重要的原因，可另为文讨论。

参考文献 

[1]"STATIC ELECTRICITY" MISCONCEPTIONS - - - William J. Beaty
[2]“Static Charge Effects and Solutions”, Technology in Brief, Ion Systems
[3]“JESD-625A Requirements for Handling Electrostatic Discharge Sensitive (ESDS) Devices.”
[4]ANSI/ESD S20.20-1999 Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Devices), ESD Association, 1999.
[5]ANSI/ESD S20.20 Paragraph 6.2.2.2 Personnel Grounding Guidance
[6]ANSI/ESD S20.20 Paragraph 6.2.3.1. Protected Areas Requirement
[7]ANSI/ESD S20.20 Paragraph 6.2.3.2. Protected Areas Guidance
[8]ESD S4.1 paragraph 8. Resistance Guidelines
[9]“Controlling Electrostatic Attraction of Particles in Production Equipment”, Douglas W. Cooper The Texwipe
Company, Upper Saddle River, N.J., Robert P. Donovan, Sandia National Laboratories, Livermore, Calif. Arnold
Steinman, IonSystems, Berkeley, Calif.
[10]“Basics of Contamination by Electrostatic Attraction”, Douglas W. Cooper, PH.D., October 1999
[11]EVERYTHING YOU EVER WANTED TO KNOW ABOUT AIR IONIZATION by Arnold Steinman MSEE
Chief Technology Officer ION Systems
[12]“Everything You Ever Wanted to Know About Air ionization”, Source Midwest Chapter, ESD Association.
[13]“Failure through electrical stress” A Study of the Mechanisms for ESD Damage to Reticles by Larry Levit1, Gaurisha Gajjar Desai2 ,Terrence Coates1,
Andrew C. Rudack2
[14]Understanding ESD Damage to Magnetoresistive Recording Heads by Al Wallash
[15]“Techniques and Methods for AHE” John T. Clack 2001 Trek Incorporated
[16]“Impact of ESD protection device trigger transient on the reliability of ultra-thin gate-oxide” by Kin P. Cheung, Bell Laboratories, Lucent Technologies
[17]“Failure analysis techniques for semiconductors and other devices” By V. Lakshminarayanan, member of the
IEEE coordinating engineer - failure analysis & reliability, Development of Telematics Centre, Bangalore, India.